![]() ![]() Clegg, “Fault equivalence in combinational logic networks,” IEEE Trans. Sonza Reorda, “Cross-fertilizing FSM verification techniques and sequential diagnosis,” Proc. Sonza Reorda, “Sequential circuit diagnosis based on formal verification techniques,” Proc. Cheung, “Model-based fault diagnosis of sequential circuits and its acceleration,” EDAC'91: IEEE European Design Auto. Cheung, “Circuit representation and diagnosis using Prolog,” ISCAS'89: IEEE International Symposium on Circuits and System, Portland, OR, pp. Davis, “Diagnostic reasoning based on structure and behavior,” Journal of Artificial Intelligence, vol. Breuer, “Fault diagnosis in sequential circuits based on effect-cause analysis,” FTCS-10: 10th Fault Tolerant Computing Symp., Kyoto (Japan), pp. Breuer, “Multiple fault diagnesis in combinational circuits based on an effect-cause analysis,” IEEE Trans. Su, “Identification of multiple stuck-type faults in combinational networks,” IEEE Trans. on Computer Aided Design, Santa Clara, CA, pp. Koopmeiners, “DIATEST: a fast diagnostic test pattern generator for combinational circuits,” ICCAD-91: IEEE Int. Sonza Reorda, “A diagnostic test pattern generation algorithm,” ITC'90: IEEE Int. ![]() Cho, “A new approach to the fault location of combinational circuits,” IEEE Trans. Hong, “Cause-effect analysis for multiple fault detection in combinational networks,” IEEE Trans. Spann, “Diagnosis of single-gate failures in combinational circuits,” IEEE Trans. Schneider, “Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits,” IEEE Trans. ![]()
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